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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos 12-bit, 3.3 v sampling adc ad7883 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram + sampling comparator control logic sar + counter clkin cs convst rd busy mode v dd low power control circuit v ina v inb v ref agnd dgnd db0 db11 12-bit dac ad7883 three state buffers features battery-compatible supply voltage: guaranteed specs for v dd of 3 v to 3.6 v 12-bit monolithic a/d converter 50 khz throughput rate 15 m s conversion time 5 m s on-chip track/hold amplifier low power power save mode: 1 mw typ normal operation: 8 mw typ 70 db snr small 24-lead soic and 0.3" dip packages applications battery powered portable systems laptop computers general description the ad7883 is a high speed, low power, 12-bit a/d converter which operates from a single +3 v to +3.6 v supply. it consists of a 5 m s track/hold amplifier, a 15 m s successive-approximation adc, versatile interface logic and a multiple-input-range circuit. the part also includes a power save feature. fast bus access times and standard control inputs ensure easy interfacing to modern microprocessors and digital signal processors. the ad7883 features a total throughput time of 20 m s and can convert full power signals up to 25 khz with a sampling fre- quency of 50 khz. in addition to the traditional dc accuracy specifications such as linearity, full-scale and offset errors, the ad7883 is also fully specified for dynamic performance parameters including har- monic distortion and signal-to-noise ratio. the ad7883 is fabricated in analog devices linear com- patible cmos (lc 2 mos) process, a mixed technology process that combines precision bipolar circuits with low power cmos logic. the part is available in a 24-pin, 0.3 inch-wide, plastic dual-in-line package (dip) as well as a small 24-lead soic package. product highlights 1. 3 v operation the ad7883 is guaranteed and tested with a supply voltage of 3 v to 3.6 v. this makes it ideal for battery-powered ap- plications where 12-bit a/d conversion is required. 2. fast conversion time 15 m s conversion time and 5 m s acquisition time allow for large input signal bandwidth. this performance is ideally suited for applications in areas such as telecommunications, audio, sonar and radar signal processing. 3. low power consumption 1 mw power consumption in the power-down mode makes the part ideally suited for portable, hand held, battery pow- ered applications.
rev. 0 C2C ad7883Cspecifications (v dd = +3 v to +3.6 v, v ref = v dd , agnd = dgnd = 0 v, f clkin = 2 mhz, mode = logic high. all specifications t min to t max unless othewise noted.) parameter b versions 1 units test conditions/comments dynamic performance 2 signal-to-noise ratio 3 (snr) 69 db min typically snr is 71 db v in = 1 khz sine wave, f sample = 50 khz total harmonic distortion (thd) C80 db typ v in = 1 khz sine wave, f sample = 50 khz peak harmonic or spurious noise C80 db typ v in = 1 khz, f sample = 50 khz intermodulation distortion (imd) second order terms C80 db typ fa = 0.983 khz, fb = 1.05 khz, f sample = 50 khz third order terms C80 db typ fa = 0.983 khz, fb = 1.05 khz, f sample = 50 khz dc accuracy resolution 12 bits all dc accuracy specifications apply for the two analog input ranges integral nonlinearity 2 lsb max differential nonlinearity 1 lsb max guaranteed monotonic full-scale error 20 lsb max bipolar zero error 12 lsb max unipolar offset error 3 lsb max analog input input voltage ranges 0 to v ref volts see figure 4 v ref volts see figure 5 input resistance 10 m w min 0 to v ref range 5/12 k w min/max 8 k w typical: v ref range reference input v ref (for specified performance) v dd v i ref 1.2 ma max logic inputs convst , rd , cs , clkin input high voltage, v inh 2.1 v min input low voltage, v inl 0.6 v max input current, i in 10 m a max v in = 0 v or v dd input capacitance, c in 4 10 pf max mode input input high voltage, v inh v dd C0.2 v input low voltage, v inl 0.2 v input current, i in 100 m a max v in = 0 v or v dd input capacitance, c in 4 10 pf max logic outputs db11Cdb0, busy output high voltage, v oh 2.4 v min i source = 200 m a output low voltage, v ol 0.4 v max i sink = 0.8 ma db11Cdb0 floating-state leakage current 10 m a max floating-state output capacitance 4 10 pf max conversion conversion time 15 m s max f clkin = 2 mhz track/hold acquisition time 5 m s max power requirements v dd +3.3 v nom +3 v to +3.6 v for specified performance i dd normal power mode @ +25 c 3 ma max typically 2 ma; mode = v dd t min to t max 4 ma max typically 2.5 ma; mode = v dd power save mode @ +25 c 400 m a max logic inputs @ 0 v or v dd ; mode = 0 v; typically 250 m a t min to t max 800 m a max logic inputs @ 0 v or v dd ; mode = 0 v; typically 300 m a power dissipation normal power mode @ +25 c 11 mw max v dd = 3.6 v: typically 8 mw; mode = v dd t min to t max 15 mw max v dd = 3.6 v: typically 9 mw; mode = v dd power save mode @ +25 c 1.5 mw max v dd = 3.6 v: typically 1 mw; mode = 0 v t min to t max 3 mw max v dd = 3.6 v: typically 1 mw; mode = 0 v notes 1 temperature range is as follows: b versions, C40 c to +85 c. 2 v in = 0 to v ref . 3 snr calculation includes distortion and noise components. 4 sample tested @ +25 c to ensure compliance. specifications subject to change without notice.
ad7883 rev. 0 C3C timing characteristics 1 limit at +25 8 c limit at t min , t max parameter (all versions) (all versions) units conditions/comments t 1 50 60 ns min convst pulse width t 2 200 200 ns max convst to busy falling edge t 3 0 0 ns min busy to cs setup time t 4 0 0 ns min cs to rd setup time t 5 0 0 ns min cs to rd hold time t 6 110 150 ns min rd pulse width t 7 2 100 140 ns max data access time after rd t 8 3 55 ns min bus relinquish time after rd 90 90 ns max notes 1 timing specifications in bold print are 100% production tested. all other times are sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 t 7 is measured with the load circuit of figure 2 and defined as the time required for an output to cross 0.8 v or 2.4 v. 3 t 8 is derived from the measured time taken by the data outputs to change by 0.5 v when loaded with the circuit of figure 2. the measured number is then extrapo- lated back to remove the effects of charging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. (v ss = +3 v to +3.6 v, v ref = v dd , agnd = dgnd = 0 v) db0 ?db11 data valid t 1 t convert t 2 t 3 t 4 t 5 t 6 t 7 t 8 convst busy cs rd three-state track/hold goes into hold figure 1. timing diagram to output pin 0.8ma +1.6v 200 m a 50pf figure 2. load circuit for access and relinquish time table i. truth table cs convt rd function 1 1 x not selected 1 j 1 start conversion g 0 1 0 enable adc data 0 1 1 data bus three stated ordering guide model temperature range package option* AD7883BN C40 c to +85 c n-24 ad7883br C40 c to +85 c r-24 *n = plastic dip; r = soic (small outline integrated circuit).
ad7883 rev. 0 C4C absolute maximum ratings* v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v agnd to dgnd . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v v ina , v inb to agnd (figure 4) . . . . . C0.3 v to v dd + 0.3 v v ina to agnd (figure 5) . . . . . . Cv dd C0.3 v to v dd + 0.3 v v ref to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v to v dd digital inputs to dgnd . . . . . . . . . . . C0.3 v to v dd + 0.3 v digital outputs to dgnd . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . +300 c power dissipation (any package) to +75 c . . . . . . . 450 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . 10 mw/ c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 23 22 21 20 19 18 17 16 15 ad7883 agnd clkin dgnd db0 db1 db2 db3 db4 db5 db6 v dd db8 v ina v inb db7 db9 db10 db11 mode cs convst rd busy v ref warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7883 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin function description pin pin no. mnemonic function 1 1v ina analog input. 1 2v inb analog input. 1 3 agnd analog ground. 1 4v ref voltage reference input. this is normally tied to v dd. 1 5 cs chip select. active low logic input. the device is selected when this input is active. 1 6 convst convert start. a low to high transition on this input puts the track/hold into hold mode and starts conversion. this input is asynchronous to the clkin and is independent of cs and rd . 1 7 rd read. active low logic input. this input is used in conjunction with cs low to enable data outputs. 1 8 busy active low logic output. this status line indicates converter status. busy is low during conversion. 1 9 clkin clock input. ttl-compatible logic input. used as the clock source for the a/d converter. the mark/ space ratio of the clock can vary from 40/60 to 60/40. 10 dgnd digital ground. 11 . . . 22 db0Cdb11 three-state data outputs. these become active when cs and rd are brought low. 23 mode mode input. this input is used to put the device into the power save mode (mode = 0 v). during normal operation, the mode input will be a logic high (mode = v dd ). 24 v dd power supply. this is nominally +3.3 v.
ad7883 rev. 0 C5C circuit information the ad7883 is a single supply 12-bit a/d converter. the part requires no external components apart from a 2 mhz external clock and power supply decoupling capacitors. it contains a 12-bit successive approximation adc based on a fast-settling voltage output dac, a high speed comparator and sar, as well as the necessary control logic. the charge balancing comparator used in the ad7883 provides the user with an inherent track- and-hold function. the adc is specified to work with sampling rates up to 50 khz. converter details the ad7883 conversion cycle is initiated on the rising edge of the convst pulse, as shown in the timing diagram of figure 1. the rising edge of the convst pulse places the track/hold amplifier into hold mode. the conversion cycle then takes between 26 and 28 clock periods. the maximum specified con- version time is 15 m s. during conversion the busy output will remain low, and the output databus drivers will be three-stated. when a conversion is completed, the busy output will go to a high level, and the result of the conversion can be read by bring- ing cs and rd low. the track/hold amplifier acquires a 12-bit input signal in 5 m s. the overall throughput time for the ad7883 is equal to the con- version time plus the track/hold acquisition time. for a 2 mhz input clock the throughput time is 20 m s. reference input for specified performance, it is recommended that the reference input be tied to v dd . the part, however, will operate with a reference down to 2.5 v though with reduced performance specifications. v ref must not be allowed to go above v dd by more than 100 mv. analog input the ad7883 has two analog input pins, v ina and v inb . figure 3 shows the input circuitry to the adc sampling comparator. the onboard attenuator network, made up of equal resistors, al- lows for various input ranges. + r v ina v inb r v dac figure 3. ad7883 input circuit the ad7883 accommodates two separate input ranges, 0 to v ref and v ref . the input configurations corresponding to these ranges are shown in figures 4 and 5. with v ref = v dd and using a nominal v dd of +3.3 v, the input ranges are 0 v to 3.3 v and 3.3 v, as shown in table ii. table ii. analog input ranges analog input input connections connection range v ref v ina v inb diagram 0 v to +3.3 v v dd v in v in figure 4 3.3 v v dd v in v ref figure 5 + r r sampling comparator v ina v inb v ref agnd 12-bit dac 0 to v ref v ref v in = 0 to v ref figure 4. 0 to v ref unipolar input configuration + r r sampling comparator agnd 12-bit dac v ina v inb v ref 0 to v ref v ref v in = v ref figure 5. v ref bipolar input configuration
ad7883 rev. 0 C6C the ad7883 has one unipolar input range, 0 v to v ref . figure 4 shows the analog input for this range. the designed code transitions occur midway between successive integer lsb val- ues (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs . . . fs C3/2 lsbs). the output code is straight binary with 1 lsb = fs/4096 = 3.3 v/ 4096 = 0.8 mv when v ref = 3.3 v. the ideal input/output transfer characteristic for the unipolar range is shown in figure 6. 1lsb = fs 4096 output code 0v 111...111 111...110 111...101 111...100 000...011 000...001 000...000 000...010 v in input voltage 1lsb fs ?1lsb + figure 6. unipolar transfer characteristics figure 5 shows the ad7883s v ref bipolar analog input con- figuration. once again the designed code transitions occur mid- way between successive integer lsb values. the output code is straight binary with 1 lsb = fs/4096 = 6.6 v/4096 = 1.6 mv. the ideal bipolar input/output transfer characteristic is shown in figure 7. a a a a aa aa aa ?s 2 fs = 10v 1lsb = fs 4096 output code 111...111 111...110 100...101 100...000 011...111 011...110 000...001 000...000 +fs 2 ?1lsb 0v v in input voltage ?lsb +1lsb figure 7. bipolar transfer characteristic clock input the ad7883 is specified to operate with a 2 mhz clock con- nected to the clkin input pin. this pin may be driven directly by cmos buffers. the mark/space ratio on the clock can vary from 40/60 to 60/40. as the clock frequency is slowed down, it can result in slightly degraded accuracy performance. this is due to leakage effects on the hold capacitor in the internal track-and-hold amplifier. figure 8 is a typical plot of accuracy versus clock frequency for the adc. 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 clock frequency ?mhz normalized linearity error figure 8. normalized linearity error vs. clock frequency track/hold amplifier the charge balanced comparator used in the ad7883 for the a/d conversion provides the user with an inherent track/hold function. the track/hold amplifier acquires an input signal to 12-bit accuracy in less than 5 m s. the overall throughput time is equal to the conversion time plus the track/hold amplifier acqui- sition time. for a 2 mhz input clock, the throughput time is 20 m s. the operation of the track/hold amplifier is essentially transpar- ent to the user. the track/hold amplifier goes from its tracking mode to its hold mode at the start of conversion, i.e., on the ris- ing edge of convst as shown in figure 1. offset and full-scale adjustment in most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. offset error can always be eliminated in the analog domain by ac coupling. full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the adc. some applications will require that the input signal range match the maximum possible dynamic range of the adc. in such applications, offset and full-scale error will have to be adjusted to zero. the following sections describe suggested offset and full-scale adjustment techniques which rely on adjusting the inherent off- set of the op amp driving the input to the adc as well as tweak- ing an additional external potentiometer as shown in figure 9.
ad7883 rev. 0 C7C + v 1 r1 10k w v ina agnd ad7883* r2 500 w r3 10k w r5 10k w r4 10k w *additional pins omitted for clarity figure 9. offset and full-scale adjust circuit unipolar adjustments in the case of the 0 v to 3.3 v unipolar input configuration, uni- polar offset error must be adjusted before full-scale error. ad- justment is achieved by trimming the offset of the op amp driving the analog input of the ad7883. this is done by apply- ing an input voltage of 0.4 mv (1/2 lsb) to v 1 in figure 9 and adjusting the op amp offset voltage until the adc output code flickers between 0000 0000 0000 and 0000 0000 0001. for full- scale adjustment, an input voltage of 3.2988 v (fsC3/2 lsbs) is applied to v 1 and r2 is adjusted until the output code flickers between 1111 1111 1110 and 1111 1111 1111. bipolar adjustments bipolar zero and full-scale errors for the bipolar input configura- tion of figure 5 are adjusted in a similar fashion to the unipolar case. again, bipolar zero error must be adjusted before full-scale error. bipolar zero error adjustment is achieved by trimming the offset of the op amp driving the analog input of the ad7883 while the input voltage is 1/2 lsb below ground. this is done by applying an input voltage of C0.8 mv (1/2 lsb) to v 1 in fig- ure 9 and adjusting the op amp offset voltage until the adc output code flickers between 0111 1111 1111 and 1000 0000 0000. for full-scale adjustment, an input voltage of 3.2988 v (fs/2C3/2 lsbs) is applied to v 1 and r2 is adjusted until the output code flickers between 1111 1111 1110 and 1111 1111 1111. dynamic specifications the ad7883 is specified and tested for dynamic performance specifications as well as traditional dc specifications such as inte- gral and differential nonlinearity. the ac specifications are re- quired for signal processing applications such as speech recognition, spectrum analysis and high speed modems. these applications require information on the adcs effect on the spectral content of the input signal. hence, the parameters for which the ad7883 is specified include snr, harmonic distor- tion, intermodulation distortion and peak harmonics. these terms are discussed in more detail in the following sections. signal-to-noise ratio (snr) snr is the measured signal-to-noise ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fs/2) excluding dc. snr is depen- dent upon the number of quantization levels used in the digiti- zation process; the more levels, the smaller the quantization noise. the theoretical signal to noise ratio for a sine wave input is given by: snr = (6.02 n + 1.76) db (1) where n is the number of bits. thus for an ideal 12-bit converter, snr = 74 db. the output spectrum from the adc is evaluated by applying a sine wave signal of very low distortion to the v in input which is sampled at a 50 khz sampling rate. a fast fourier transform (fft) plot is generated from which the snr data can be ob- tained. figure 10 shows a typical 2048 point fft plot of the ad7883 with an input signal of 2.5 khz and a sampling fre- quency of 50 khz. the snr obtained from this graph is 71 db. it should be noted that the harmonics are taken into account when calculating the snr. 0 ?0 ?0 ?0 ?20 0 2.5 25 frequency khz signal amplitude dbs input frequency = 2.5khz sample frequency = 50khz snr = 71.4db t a = +25c figure 10. fft plot effective number of bits the formula given in equation 1 relates the snr to the number of bits. rewriting the formula, as in equation 2, it is possible to get a measure of performance expressed in effective number of bits (n). n = snr 1.76 6.02 (2) the effective number of bits for a device can be calculated di- rectly from its measured snr. figure 11 shows a plot of effective number of bits versus input frequency for an ad7883 with a sampling frequency of 50 khz. the effective number of bits typically remains better than 11.5 for frequencies up to 12 khz.
ad7883 rev. 0 C8C 12 11.5 11 10.5 10 input frequency ?khz 15 25 effective number of bits 20 10 5 sample frequency = 50khz t a = +25 c figure 11. effective number of bits vs. frequency total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the ad7883, thd is defined as: thd = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 (3) where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonic. the thd is also derived from the fft plot of the adc output spectrum. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m nor n are equal to zero. for example, the second or- der terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). using the ccif standard where two input frequencies near the top end of the input bandwidth are used, the second and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the in- termodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion prod- ucts to the rms amplitude of the fundamental expressed in dbs. in this case, the input consists of two, equal amplitude, low dis- tortion, sine waves. figure 12 shows a typical imd plot for the ad7883. 0 ?0 ?0 ?0 ?20 0 2.5 25 frequency ?khz signal amplitude ?dbs input frequency f1 = 0.983khz f2 = 1.05khz sample frequency = 50khz ta = +25 c imd all terms = 81.5db 2nd order terms = 83.6db 3rd order terms = 85.4db figure 12. imd plot peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification will be determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor the peak will be a noise peak.
ad7883 rev. 0 C9C application hints good printed circuit board (pcb) layout is as important as the circuit design itself in achieving high speed a/d performance. the ad7883s comparator is required to make bit decisions on an lsb size of 0.8 mv. to achieve this, the designer must be conscious of noise both in the adc itself and in the preceding analog circuitry. switching mode power supplies are not recom- mended, as the switching spikes will feed through to the com- parator causing noisy code transitions. other causes of concern are ground loops and digital feedthrough from microprocessors. these are factors which in fluence any adc, and a proper pcb layout which minimizes these effects is essential for best performance. layout hints ensure that the layout for the printed circuit board has the digi- tal and analog signal lines separated as much as possible. take care not to run digital tracks alongside analog signal tracks. guard (screen) the analog input with agnd. establish a single point analog ground (star ground) separate from the logic system ground at the ad7883 agnd pin or as close as possible to the ad7883. connect all other grounds and the ad7883 dgnd to this single analog ground point. do not connect any other digital grounds to this analog ground point. low impedance analog and digital power supply common re- turns are essential to low noise operation of the adc, so make the foil width for these tracks as wide as possible. the use of ground planes minimizes impedance paths and also guards the analog circuitry from digital noise. noise keep the input signal leads to v in and signal return leads from agnd as short as possible to minimize input noise coupling. in applications where this is not possible, use a shielded cable be- tween the source and the adc. reduce the ground circuit im- pedance as much as possible since any potential difference in grounds between the signal source and the adc appears as an error voltage in series with the input signal. v+ + c1 10 m f c2 0.1 m f ic1 analog input v+ v ab v ab lk2 lk3 to adc lk1 skt1 c3 10 m f c4 0.1 m f v+ v dd figure 13. analog input buffering analog input buffering to achieve specified performance, it is recommended that the analog input (v ina , v inb ) be driven from a low impedance source. this necessitates the use of an input buffer amplifier. the choice of op amp will be a function of the particular appli- cation and the desired analog input range. the simplest configuration is the 0 v to v ref range of figure 4. a single supply op amp is recommended for such an implemen- tation. this will allow for operation of the ad7883 in the 0 to v ref unipolar range without supplying an external supply to v+ and vC of the op amp. recommended single-supply op amps are the op-195 and ad820. in bipolar operation, positive and negative supplies must be connected to v+ and vC of the op amp. the ad711 is a general purpose op amp which could be used to drive the analog input of the ad7883, in this input range.
ad7883 rev. 0 C10C power-down control (mode input) the ad7883 is designed for systems which need to have mini- mum power consumption. this includes such applications as hand held, portable battery powered systems and remote moni- toring systems. as well as consuming minimum power under normal operating conditions, typically 8 mw, the ad7883 can be put into a power-down or sleep mode when not required to convert signals. when in this power-down mode, the ad7883 consumes 1 mw of power. the ad7883 is powered down by bringing the mode input pin to a logic low in conjunction with keeping the rd input control high. the ad7883 will remain in the power-down mode until mode is brought to a logic high again. the mode input should be driven with cd4000 or hcmos logic levels. it is recommended that one dummy conversion be imple- mented before reading conversion data from the ad7883 after it has been in the powerdown mode. this is required to reset all internal logic and control circuitry. allow one clock cycle before doing the dummy conversion. in a remote monitoring system where, say, 10 conversions are required to be taken with a sam- pling interval of 1 second, an additional 11th conversion must be carried out. figure 14 gives a plot of power consumption as a function of time for such operation. the total conversion time for each cycle is 11 20 m s (where 20 m s is the time taken for a single conversion) corresponding to 2.2 10 C4 secs. 0 1 2 time ?secs power consumption ?mw 8 1 converting power-down converting power-down 2.2 x 10 ? figure 14. power consumption for normal operation and power-down operation vs. time hence: average power = power converting + power power-down = {8 mw (2.2 10 C4 )} + {1 mw (0.9998)} = 1.0015 mw
ad7883 rev. 0 C11C outline dimensions dimensions shown in inches and (mm). 24-lead plastic dip (n-24) 24-lead soic (r-24)
c1699C24C9/92 printed in u.s.a. C12C

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